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general description the max8553 is a 4.5v to 28v input-voltage, synchro- nous step-down controller that provides a complete power-management solution for ddr memory. the max8553 generates 1/2 v refin voltage for vtt and vttr. the vtt and vttr tracking voltages are main- tained within 1% of 1/2 v refin . the MAX8554 is a 4.5v to 28v input voltage, nontracking step-down controller with a low 0.6v feedback threshold voltage. the max8553/ MAX8554 use maxim? proprietary quick-pwm archi- tecture for fast transient response and operate with selectable pseudo-fixed frequencies. both controllers can operate without an external bias supply. the controllers operate in synchronous-rectification mode to ensure balanced current sourcing and sinking capabili- ty of up to 25a. the max8553/MAX8554 also provide up to 95% efficiency, making them ideal for server and point- of-load applications. additionally, a low 5? shutdown current allows for longer battery life in notebook applica- tions. lossless current monitoring is achieved by monitor- ing the low-side mosfet? drain-to-source voltage. the max8553/MAX8554 have an adjustable foldback current limit to withstand a continuous output overload and short circuit. digital soft-start provides control of inrush current during power-up. overvoltage protection shuts the con- verter down and discharges the output capacitor. the max8553/MAX8554 come in space-saving 16-pin qsop packages. applications wide-input power supplies servers and storage applications asic and cpu core voltages notebook and lcd-pc power supplies ddr i and ddr ii memory power supplies agtl bus termination supplies features up to 25a output-current capability quick-pwm control for fast loop response up to 95% efficiency 4.5v to 28v input voltage range no external bias supply required 0 to 3.6v input refin range (max8553) automatically sets vtt and vttr to within 1% of 1/2 v refin - (max8553) low 0.6v feedback threshold (MAX8554) 200khz/300khz/400khz/550khz selectable switching frequencies adjustable foldback current limit overvoltage protection digital soft-start max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications ________________________________________________________________ maxim integrated products 1 ordering information max8553 dh en/hsd +5v pok vin vout vttr v+ refin lx dl vttr gnd pok refin vl bst v+ ref ilim fsel pgnd vtt part temp range pin-package max8553 eee -40 c to +85 c 16 qsop MAX8554 eee -40 c to +85 c 16 qsop typical operating circuit 19-3017; rev 0; 10/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations appear at end of data sheet. quick-pwm is a trademark of maxim integrated products, inc.
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v v+ = v hsd = +12v, v en/hsd = v refin = +2.5v, v en = +5v, c vl = 4.7f, c vttr = 1f, c ref = 0.22f, v fsel = 0v, ilim = vl, pgnd = lx = gnd, bst = vl, t a = 0? to +85?. typical values are at t a = +25 c, unless otherwise specified.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+, en/hsd, en, hsd to gnd...............................-0.3v to +30v pgnd to gnd .......................................................-0.3v to +0.3v vtt, refin, pok, out, fb, vl to gnd...................-0.3v to +6v ref, vttr, dl, ilim, fsel to gnd ............-0.3v to (v vl + 0.3v) lx to pgnd ...............................................................-2v to +30v bst to gnd ............................................................-0.3v to +36v dh to lx ...................................................................-0.3v to +6v lx to bst..................................................................-6v to +0.3v ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70 c) 16-pin qsop (derated 8.3mw/ c above +70 c) ........667mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter conditions min typ max units v+ input voltage range vl not connected to v+ 6 28 v v+ input voltage range vl connected to v+ 4.5 5.5 v en/hsd input voltage range max8553 enabled 1.5 28.0 v en input voltage range MAX8554 enabled 1.5 28.0 v en input current 23a hsd input voltage range MAX8554 enabled 1.5 28.0 v hsd input current 20 40 a refin input voltage range 0 3.6 v v+ supply current (max8553) v vtt = +1.35v 0.8 1.2 ma v+ supply current (MAX8554) v fb = 630mv 0.62 0.90 ma refin supply current 125 250 a en/hsd supply current 510a vl supply current v vl = v v+ = 5.5v, v vtt = +1.35v 0.8 1.2 ma v+ shutdown supply current en/hsd = gnd 3 5 a refin shutdown supply current en/hsd = gnd 1 a vl shutdown supply current v vl = v v+ = +5.5v, v en/hsd = 0v 5 12 a vl undervoltage-lockout threshold rising edge, typical hysteresis = 40mv 4.05 4.25 4.40 v vtt vtt input bias current v vtt = +1.25v -0.15 0 a vtt feedback voltage range 0 1.8 v v refin = v en/hsd = +1.8v 49.5 50 50.5 vtt feedback voltage accuracy v refin = v en/hsd = +3.6v 49.5 50 50.5 % v re fin fb input bias current MAX8554, v fb = +600mv -0.15 0 a
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications _______________________________________________________________________________________ 3 electrical characteristics (continued) (v v+ = v hsd = +12v, v en/hsd = v refin = +2.5v, v en = +5v, c vl = 4.7f, c vttr = 1f, c ref = 0.22f, v fsel = 0v, ilim = vl, pgnd = lx = gnd, bst = vl, t a = 0 c to +85 c. typical values are at t a = +25 c, unless otherwise specified.) parameter conditions min typ max units fb regulation voltage MAX8554, v out = +2.5v, fsel unconnected 0.598 0.607 0.616 v output adjust range MAX8554 (note 1) 0.6 3.5 v vtt line regulation v en/hsd 10%, v vtt = +1.25v, i out = 0a 0.325 % fb line regulation MAX8554, v hsd 10%, v out = +2.5v, i out = 0a, fsel unconnected 0.325 % vtt load regulation 0 < i out < +7a, v vtt = +1.25v 0.2 % fb load regulation MAX8554, 0 < i out < +7a, v out = +2.5v, fsel unconnected 0.2 % reference reference output voltage v v+ = v vl = +4.5 to +5.5v, i ref = 0 1.97 2.00 2.03 v reference load regulation v v+ = v vl = +5v, i ref = 0 to 50a 10 mv reference uvlo v v+ = v vl = +5v, reference rising, hysteresis = 27mv 1.5 1.6 1.7 v vttr vttr output voltage range 0 1.8 v i vttr = -5ma to +5ma 49.5 50 50.5 i vttr = -25ma to +25ma, v refin = +1.8v 49 50 51 vttr output accuracy i vttr = -25ma to +25ma, v refin = +3.6v 49.5 50 50.5 % v re fin thermal shutdown rising temperature, typical hysteresis = 15 c +160 c soft-start ilim ramp period ramps the ilim trip threshold from 20% to 100% in 20% increments 0.8 1.7 3.0 ms output predischarge period rising edge of en/hsd to the start of internal digital soft-start 0.8 1.7 3.0 ms oscillator fsel = vl 200 fsel = unconnected 300 fsel = ref 400 oscillator frequency fsel = gnd 550 khz fsel = vl 2.18 2.5 2.83 fsel unconnected 1.45 1.67 1.89 fsel = ref 1.09 1.25 1.41 on-time max8553, v vtt = +1.25v (note 2) fsel = gnd 0.82 0.91 1.00 s fsel = vl 0.89 1.02 1.16 fsel unconnected 0.61 0.71 0.80 fsel = ref 0.43 0.49 0.56 on-time MAX8554, v out = +2.5v (note 2) fsel = gnd 0.33 0.37 0.41 s off-time (note 2) 350 400 ns
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 4 _______________________________________________________________________________________ electrical characteristics (continued) (v v+ = v hsd = +12v, v en/hsd = v refin = +2.5v, v en = +5v, c vl = 4.7f, c vttr = 1f, c ref = 0.22f, v fsel = 0v, ilim = vl, pgnd = lx = gnd, bst = vl, t a = 0 c to +85 c. typical values are at t a = +25 c, unless otherwise specified.) parameter conditions min typ max units current limit lx to pgnd, ilim = vl 80 100 115 lx to pgnd, r ilim = 100k ? 35 50 65 current-limit threshold (positive direction) lx to pgnd, r ilim = 400k ? 160 200 230 mv current-limit threshold (negative direction) lx to pgnd, ilim = vl, with respect to positive current-limit threshold -130 -110 -90 % ilim input current 5a fault detection max8553 (v refin > +1v) 57 60 63 % v re fin max8553 (v refin +1v) 0.576 0.600 0.624 overvoltage threshold MAX8554 0.696 0.720 0.744 v vl regulator output voltage +6v < v v+ <+28v, 1ma < i vl < 35ma 4.80 5.0 5.33 v line regulation +6v < v v+ < +28v, i vl = 10ma 0.2 % rms output current 35 ma bypass capacitor esr < 100m ? 2.2 f driver dh gate-driver on-resistance v bst - v lx = +5v 1.4 2.5 ? dl gate-driver on-resistance (source) dl high state 1.6 3.0 ? dl gate-driver on-resistance (sink) dl low state 0.75 1.25 ? dl rising 32 dead time dl falling 30 ns fsel logic logic input current -3 +3 a logic low (gnd) 0.5 v logic ref level fsel = ref 1.65 2.35 v logic float level fsel unconnected 3.15 3.85 v logic vl level fsel = vl v vl - 0.4 v en/hsd or en logic en/hsd or en shutdown current max i en/hsd for v en/hsd < +0.8v or v en < +0.8v 0.5 3.0 a logic high v vl = v v+ = +4.5 to +5.5v, 100mv hysteresis 1.5 v logic low v vl = v v+ = +4.5 to +5.5v 0.8 v
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications _______________________________________________________________________________________ 5 electrical characteristics (continued) (v v+ = v hsd = +12v, v en/hsd = v refin = +2.5v, v en = +5v, c vl = 4.7f, c vttr = 1f, c ref = 0.22f, v fsel = 0v, ilim = vl, pgnd = lx = gnd, bst = vl, t a = 0 c to +85 c. typical values are at t a = +25 c, unless otherwise specified.) parameter conditions min typ max units power-ok output upper vtt and vttr threshold max8553 55 56 57 % v re fin lower vtt and vttr threshold max8553 43 44 45 % v re fin upper threshold MAX8554 0.646 0.672 0.698 v lower threshold MAX8554 0.504 0.528 0.552 v pok output low level i sink = 2ma 0.4 v pok output high leakage v pok = +5v 5 a electrical characteristics (v v+ = v hsd = +12v, v en/hsd = v refin = +2.5v, v en = +5v, c vl = 4.7f, c vttr = 1f, c ref = 0.22f, v fsel = 0, ilim = vl, pgnd = lx = pok = gnd, bst = vl, t a = -40 c to +85 c , unless otherwise specified.) (note 3) parameter conditions min max units v+ input voltage range vl not connected to v+ 6 28 v v+ input voltage range vl connected to v+ 4.5 5.5 v en/hsd input voltage range max8553 enabled 1.5 28.0 v en input voltage range MAX8554 enabled 1.5 28.0 v en input current 3a hsd input voltage range MAX8554 enabled 1.5 28.0 v hsd input current 40 a refin input voltage range 0 3.6 v v+ supply current (max8553) v vtt = +1.35v 1.2 ma v+ supply current (MAX8554) v fb = 630mv 0.90 ma refin supply current 250 a en/hsd supply current 10 a vl supply current v vl = v v+ = 5.5v, v vtt = +1.35v 1.2 ma v+ shutdown supply current en/hsd = gnd 5 a refin shutdown supply current en/hsd = gnd 1 a vl shutdown supply current v vl = v v+ = +5.5v, v en/hsd = 0v 12 a vl undervoltage-lockout threshold rising edge, typical hysteresis = 40mv 4.05 4.40 v vtt vtt input bias current v vtt = +1.25v -0.2 0 a vtt feedback voltage range 0 1.8 v v refin = v en/hsd = +1.8v 49.5 50.5 vtt feedback voltage accuracy v refin = v en/hsd = +3.6v 49.5 50.5 % v re fin fb input bias current MAX8554, v fb = +600mv -0.2 0 a fb regulation voltage MAX8554, v out = +2.5v, fsel unconnected 0.598 0.616 v output adjust range MAX8554 (note 1) 0.6 3.5 v
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 6 _______________________________________________________________________________________ electrical characteristics (continued) (v v+ = v hsd = +12v, v en/hsd = v refin = +2.5v, v en = +5v, c vl = 4.7f, c vttr = 1f, c ref = 0.22f, v fsel = 0, ilim = vl, pgnd = lx = pok = gnd, bst = vl, t a = -40 c to +85 c , unless otherwise specified.) (note 3) parameter conditions min max units reference reference output voltage v v+ = v vl = +4.5 to +5.5v, i ref = 0 1.97 2.03 v reference load regulation v v+ = v vl = +5v, i ref = 0 to 50a 10 mv reference uvlo v v+ = v vl = +5v, reference rising, hysteresis = 27mv 1.5 1.7 v vttr vttr output voltage range 0 1.8 v i vttr = -5ma to +5ma 49.5 50.5 i vttr = -25ma to +25ma, v refin = +1.8v 49 51 vttr output accuracy i vttr = -25ma to +25ma, v refin = +3.6v 49.5 50.5 % v re fin soft-start ilim ramp period ramps the ilim trip threshold from 20% to 100% in 20% increments 0.8 3.0 ms output predischarge period rising edge of en/hsd to the start of internal digital soft-start 0.8 3.0 ms oscillator fsel = vl 2.18 2.83 fsel unconnected 1.45 1.89 fsel = ref 1.09 1.41 on-time max8553, v vtt = +1.25v (note 2) fsel = gnd 0.82 1.00 s fsel = vl 0.89 1.16 fsel unconnected 0.61 0.80 fsel = ref 0.43 0.56 on-time MAX8554, v out = +2.5v (note 2) fsel = gnd 0.33 0.41 s off-time (note 2) 420 ns current limit lx to pgnd, ilim = vl 80 115 lx to pgnd, r ilim = 100k ? 30 65 current-limit threshold (positive direction) lx to pgnd, r ilim = 400k ? 150 230 mv current-limit threshold (negative direction) lx to pgnd, ilim = vl, with respect to positive current-limit threshold -130 -90 % ilim input current a fault detection max8553 (v refin > +1v) 57 63 % max8553 (v refin +1v) 0.576 0.624 overvoltage threshold MAX8554 0.696 0.744 v vl regulator output voltage +6v < v v+ < +28v, 1ma < i vl < 35ma 4.80 5.33 v rms output current 35 ma bypass capacitor esr < 100m ? 2.2 f
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications _______________________________________________________________________________________ 7 electrical characteristics (continued) (v v+ = v hsd = +12v, v en/hsd = v refin = +2.5v, v en = +5v, c vl = 4.7f, c vttr = 1f, c ref = 0.22f, v fsel = 0, ilim = vl, pgnd = lx = pok = gnd, bst = vl, t a = -40 c to +85 c , unless otherwise specified.) (note 3) parameter conditions min max units driver dh gate-driver on-resistance v bst - v lx = +5v 2.5 ? dl gate-driver on-resistance (source) dl high state 3.0 ? dl gate-driver on-resistance (sink) dl low state 1.25 ? fsel logic logic input current -3 +3 a logic low (gnd) 0.5 v logic ref level fsel = ref 1.65 2.35 v logic float level fsel unconnected 3.15 3.85 v logic vl level fsel = vl v vl - 0.4 v en/hsd or en logic en/hsd or en shutdown current max i en/hsd for v en/hsd < +0.8v or v en < +0.8v 0.5 3.0 a logic high v vl = v v+ = +4.5 to +5.5v, 100mv hysteresis 1.5 v logic low v vl = v v+ = +4.5 to +5.5v 0.8 v power-ok output upper vtt, and vttr threshold max8553 55 57 % v re fin lower vtt, and vttr threshold max8553 43 45 % v re fin upper threshold MAX8554 0.646 0.698 v lower threshold MAX8554 0.504 0.552 v pok output low level i sink = 2ma 0.4 v pok output high leakage v pok = +5v 5 a note 1: consult factory for applications that require higher than 3.5v output. note 2: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx forced to 0v, bst forced to 5v, and a 250pf capacitor connected from dh to lx. actual in-circuit times may differ due to mosfet switching speeds. note 3: specifications to -40 c are guaranteed by design and are not production tested.
1.19 1.23 1.21 1.27 1.25 1.29 1.31 04 268 load regulation (circuit of figure 2) max8553/4 toc09 load current (a) output voltage (v) vtt connected as shown in figure 2 vtt connected to the output max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 8 _______________________________________________________________________________________ typical operating characteristics (v v+ = 12v, v out = 1.8v, circuit of figure 1, t a = +25 c, unless otherwise noted.) 100 30 0.1 1.0 10.0 efficiency vs. load current (circuit of figure 2) 60 max8553/4 toc01 load current (a) efficiency (%) 70 40 50 80 90 v in = 1.8v v out = 0.9v v in = 2.5v v out = 1.25v 0.1 10.0 100.0 efficiency vs. load current (circuit of figure 1) max8553/4 toc02 load current (a) efficiency (%) 1.0 100 30 40 50 60 70 90 80 v out = 1.8v v out = 2.5v 400 450 550 500 600 650 -8 -4 -2 -6 02468 switching frequency vs. output current (circuit of figure 2) max8553/4 toc03 output current (a) switching frequency (khz) 200 240 220 280 260 300 320 6 8 10 12 14 16 18 20 22 24 26 28 switching frequency vs. input voltage (circuit of figure 3) max8553/4 toc04 input voltage (v) switching frequency (khz) 160 180 170 200 190 210 220 -40 -15 10 35 60 85 frequency vs. temperature max8553/4 toc05 temperature ( c) frequency (khz) 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.5 5.0 4 8 12 16 20 24 28 MAX8554 shutdown supply current vs. input voltage max8553/4 toc06 input voltage (v) shutdown supply current ( a) v+ = hsd, en = gnd 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.5 5.0 4 8 12 16 20 24 28 max8553 shutdown supply current vs. input voltage max8553/4 toc07 input voltage (v) shutdown supply current ( a) en = gnd 1.74 1.78 1.76 1.82 1.80 1.84 1.86 0 4.0 8.0 12.0 16.0 20.0 load regulation (circuit of figure 1) max8553/4 toc08 load current (a) output voltage (v)
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v v+ = 12v, v out = 1.8v, circuit of figure 1, t a = +25 c, unless otherwise noted.) load transient 0a to 20a to 0a (circuit of figure 1) max8553/4 toc10 40 s/div i out 10a/div 100mv/div ac-coupled v out load transient -8a to +8a to -8a (circuit of figure 2) max8553/4 toc11 40 s/div vtt connected to the output v out 0 5a/div 20mv/div ac-coupled i out load transient -8a to +8a to -8a (circuit of figure 2) max8553/4 toc12 40 s/div vtt connected as shown in figure 2 v out 0 5a/div 20mv/div ac-coupled i out switching waveforms with 20a load (circuit of figure 1) max8553/4 toc13 2 s/div v lx i l 10a/div 0 5v/div 20mv/div ac-coupled v out
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 10 ______________________________________________________________________________________ typical operating characteristics (continued) (v v+ = 12v, v out = 1.8v, circuit of figure 1, t a = +25 c, unless otherwise noted.) power-up waveforms with 20a load (circuit of figure 1) max8553/4 toc14 2ms/div v in i l 10a/div 10v/div 0 1v/div 5v/div v pok v out power-down waveforms with 20a load (circuit of figure 1) max8553/4 toc15 1ms/div v in i l 10a/div 10v/div 0 1v/div 5v/div v pok v out startup/shutdown waveforms with 20a load (circuit of figure 1) max8553/4 toc16 2ms/div v en i in 2a/div 5v/div 0 1v/div 5v/div v pok v out short circuit and recovery (circuit of figure 1) max8553/4 toc17 200 s/div v lx i l 20v/div 5a/div 1v/div 0v 0a v out
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications ______________________________________________________________________________________ 11 pin description pin max8553 MAX8554 function en/hsd enable/high-side drain. connect to the high-side n-channel mosfet drain through a 5.1k ? resistor for normal operation. connect to gnd for low-power shutdown (figure 2). if the enable function is not used, connect en/hsd directly to the high-side n-channel mosfet drain. 1 hsd high-side drain. connect to the high-side n-channel mosfet drain for normal operation. refin reference input. an applied voltage at refin sets v vtt and v vttr to 1/2 v refin . refin voltage range is from 0 to +3.6v. 2 en enable. drive en high to enable the output. drive en low to shut down the ic. if the enable function is not used, connect en to v+. 3 pok pok power-ok output. pok is an open-drain output and is logic high when both vtt and vttr are within 12% of regulation. pok is pulled low in shutdown. vtt vtt feedback input. connect to vtt output. 4 fb output feedback. connect to the center of a resistor-divider between the output and ground to set the output voltage. fb threshold is 0.6v. 5 ilim ilim current-limit threshold adjustment. connect a resistor from ilim to gnd to set the current-limit threshold, or connect ilim to vl for the default setting. see the setting the current limit section. 6 fsel fsel frequency select. selects the switching frequency. see tables 1 and 2 for configuration of fsel. 7 ref ref reference. connect a 0.22f or greater capacitor from ref to gnd. 8 gnd gnd ground vttr vttr reference output. connect a 1f or greater capacitor from vttr to gnd. vttr is capable of sourcing and sinking up to 25ma. 9 out output voltage. connect directly to the output. out senses the output voltage to determine the on-time for the high-side switching mosfet. 10 v+ v+ input supply voltage. supply input for the vl regulator. bypass with a 0.22f or greater capacitor. 11 vl vl internal regulator output. connect a 2.2f or greater capacitor from vl to gnd. vl can be connected to v+ if the operating range is from +4.5v to +5.5v. 12 dl dl low-side mosfet gate drive. connect to the gate of the low-side n-channel mosfet. dl is low in shutdown or in undervoltage lockout. 13 pgnd pgnd power ground 14 bst bst bootstrapped supply. drives high-side n-channel mosfet. connect a 0.1f or greater capacitor from bst to lx. 15 dh dh high-side mosfet gate drive. connect to the high-side n-channel mosfet gate. dh is low in shutdown or in undervoltage lockout. 16 lx lx inductor switching node
functional diagrams q s r q trig one-shot trig q one-shot ton on-time compute vtt latch q rs vttr vtt pok error comp ovp 60% 56% 50% 44% vl 0.6v 5v reg 2v ref /10 5 a max8553 fsel pok refin en/hsd vttr gnd ref vl vtt pgnd dl v+ lx dh bst ilim max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 12 ______________________________________________________________________________________
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications ______________________________________________________________________________________ 13 functional diagrams (continued) q s r q trig one-shot trig q one-shot ton on-time compute out latch q rs fb pok error comp ovp vl 5v reg 2v ref /10 5 a MAX8554 fsel pok gnd ref vl fb pgnd dl v+ lx dh bst ilim en hsd 0.672v 0.528v 0.720v 0.600v
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 14 ______________________________________________________________________________________ typical application circuits c4 0.47 f 10v q1 irf7832 q2 2xirf7832 l1 1.0 h 30a r6 1 ? c8 4700pf optional r2 19.1k ? r3 6.04k ? c6 3x470 f 4v c5 10 f 6.3v vout pgnd c3 4.7 f 6.3v d1 cmpsh-3 2.5v at 20a 12v vin c2 2x470 f 16v c1 10 f 16v MAX8554 vl pok r1 20k ? on off c7 0.22 f 10v r4 25.5k ? r5 110k ? pok v+ en hsd ref ilim gnd fsel vl bst dh lx dl pgnd out fb figure 1. typical application circuit 1: 12v input, 2.5v output at up to 20a with 200khz switching frequency c4 0.47 f 6.3v q1 irf7821 q2 irf7821 l1 0.68 h 9a c5 10 f 6.3v c6 4x470 f 2v vout pgnd c3 4.7 f 6.3v d1 cmpsh-3 1.25v at 8a 2.5v vin c2 2x330 f 6v c1 10 f 6.3v max8553 pok r3 20k ? c8 0.22 f 10v 6v to 28v r1 143k ? r6 54.9k ? pok v+ refin en/hsd ref ilim gnd fsel vl bst dh lx dl pgnd vtt vttr vttr c7 1 f 6.3v vl v+ refin c9 0.47 f 25v sdn r5 100k ? q3 2n7002k to v out r2 5.1k ? r4 0.002 ? c10 2200 f r7 3 ? r8 20 ? c11 1 f figure 2. typical application circuit 2: 2.5v input, 1.25v vtt at up to 8a, and 1.25v vttr at up to 25ma with 550khz switching
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications ______________________________________________________________________________________ 15 detailed description internal linear regulator an internal regulator produces the +5v supply (vl) that powers the pwm controller, mosfet driver, logic, refer- ence, and other blocks within the ic. this +5v low- dropout (ldo) linear regulator supplies up to 35ma for mosfet gate-drive and external loads. for supply volt- ages between +4.5v and +5.5v, connect vl to v+. this bypasses the vl regulator, which improves efficiency and allows the ic to function at lower input voltages. on-time one-shot and switching frequency the heart of the pwm is the one-shot that sets the high- side switch on-time. this fast, low-jitter, adjustable one- shot includes circuitry that varies the on-time in response to both input and output voltages. the high- side switch on-time is inversely proportional to the input voltage as measured by the en/hsd (hsd for the MAX8554) input, and is directly proportional to the out- put voltage. this algorithm results in a nearly constant switching frequency despite the lack of a fixed-fre- quency clock generator. the switching frequency can be selected to avoid noise-sensitive regions such as the 455khz if band. also, with a constant switching fre- quency, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. the general formula for the max8553 on-time (t on ) is: where v en/hsd and v out are the voltages measured at en/hsd and the output, respectively, and k = 1.7s. the value of n depends on the configuration of fsel and is listed in table 1. for the MAX8554, the general formula for on-time (t on ) is: where v hsd and v out are the voltages measured at hsd and the output, respectively, and k = 1.7s. the value of n depends on the configuration of fsel and is listed in table 2. tkn v v on hsd out = 1 tkn v v on en hsd out / = 1 c4 0.47 f 10v q1 irf7807v q2 irf7821 l1 2.5 h 10a r6 3 ? c8 2200pf r2 12.1k ? r3 6.04k ? c6 2x470 f 4v c5 10 f 6.3v vout pgnd c3 4.7 f 6.3v d1 cmpsh-3 1.8v at 8a 17v to 21v vin c2 470 f 16v c1 10 f 16v MAX8554 vl pok r1 20k ? on off c7 0.22 f 10v r4 61.9k ? r5 80.6k ? pok v+ en hsd ref ilim gnd fsel vl bst dh lx dl pgnd out fb figure 3. typical application circuit 3: 19v input, 1.8v output at up to 8a with 300khz switching frequency
this algorithm results in a nearly constant switching fre- quency despite the lack of a fixed-frequency clock generator. the actual switching frequency, which is given by the following equation, varies slightly due to the voltage drop across the on-resistance of the mosfets and the dc resistance of the output inductor: where d is the duty cycle: where i o is the output current, r dsonl is the on-resis- tance of the low-side mosfet, r dsonh is the on-resis- tance of the high-side mosfet, and r dc is the dc resistance of the output inductor. the ideal switching fre- quency for v refin = 2.5v is about 550khz. switching fre- quency increases for positive (sourcing) load current and decreases for negative (sinking) load current, due to the changing voltage drop across the low-side mosfet, which changes the inductor-current discharge ramp rate. the on-times guaranteed in the electrical characteristics are also influenced by switching delays caused by the loading effect of the external power mosfets. the switching frequency can also be adjusted to a value other than the preset frequencies by adding a resistor voltage-divider at hsd. see the adjusting the switching frequency section. vttr reference (max8553 only) the max8553 s vttr output is capable of sourcing or sinking up to 25ma of current. the vttr output voltage is one-half of the voltage applied to refin. bypass vttr with at least a 1f ceramic capacitor. voltage reference the voltage at ref is nominally 2.00v. connect a 0.22f ceramic bypass capacitor between ref and gnd. en and hsd (MAX8554 only) en is a logic input used to enable or shut down the MAX8554. drive en high or connect to v+ to enable the output. drive en low to place the MAX8554 in low- power shutdown mode, reducing input current to less than 5a (typ). hsd senses the input voltage at the drain of the high-side mosfet, which is used to set the high-side mosfet on- time. for normal operation, connect hsd to the drain of the high-side mosfet. en/hsd function (max8553 only) in order to reduce pin count and package size, the max8553 features a dual-function input pin, en/hsd. when en/hsd is pulled to ground, the internal circuitry powers off, reducing current consumption to less than 5a (typ). to enable normal operation, connect en/hsd to the drain of the high-side mosfet through a 5.1k ? resistor ( figure 2). in this configuration, en/hsd becomes an input that monitors the high-side mosfet drain voltage (converter input voltage) and uses that measurement to calculate the appropriate on-time for the converter. if the enable function is not used, connect en/hsd directly to the high-side mosfet drain. d vir r vir r out o dsonl dc hsd o dsonl dsonh = ++ () + () - f d tkn s on =? 1 max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 16 ______________________________________________________________________________________ table 1. configuration of fsel (max8553) fsel connected to n t on (s) frequency (khz) condition ground 1.07 0.91 550 v out / v en/hsd = 0.5 ref 1.33 1.15 400 v out / v en/hsd = 0.5 floating 2.00 1.70 300 v out / v en/hsd = 0.5 vl 3.00 2.55 200 v out / v en/hsd = 0.5 table 2. configuration of fsel (MAX8554) fsel connected to n t on (s) frequency (khz) condition ground 1.07 0.37 550 v hsd = 12v, v out = 2.5v ref 1.33 0.49 400 v hsd = 12v, v out = 2.5v floating 2.00 0.71 300 v hsd = 12v, v out = 2.5v vl 3.00 1.02 200 v hsd = 12v, v out = 2.5v
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications ______________________________________________________________________________________ 17 predischarge mode the max8553/MAX8554 discharge the output to gnd before the digital soft-start begins. when en/hsd (en) is pulled high, the max8553 (MAX8554) starts an inter- nal counter, and forces v dl to v vl . this discharges the output to gnd through the low-side mosfet. if the out- put voltage is above ground before enable, the output voltage goes slightly negative due to energy stored in the output lc. if the load cannot tolerate a negative volt- age, place a power schottky diode from the output to pgnd (anode to pgnd) to act as a reverse-polarity clamp. the period for this discharge mode is 1.7ms. both the buck controller and the vttr buffer are turned off during this period. after the predischarge period, both the buck controller and the vttr buffer are turned on and go through soft-start. digital soft-start the digital soft-start allows a gradual increase of the internal current-limit level during startup to reduce the input surge current. the max8553/MAX8554 divide the soft-start period into five phases. during the first phase, the controller limits the current limit to only 20% of the full current limit. if the output does not reach the regula- tion within 425s, soft-start enters the second phase and the current limit is increased by another 20%. this process repeats until the maximum current limit is reached (after 1.7ms) or when the output reaches the nominal regulation voltage, whichever occurs first. adding a capacitor in parallel with the external ilim resistor creates a continuously adjustable analog soft- start function. if the foldback current-limiting feature is implemented in the application circuit, the maximum current limit is also a function of the output voltage and the resistors connected to ilim. power-good output (pok) pok is the open-drain output of the internal window comparators that continuously monitor vtt and vttr for the max8553 and fb for the MAX8554. pok is actively held low in shutdown, and becomes high impedance when the outputs are within 12% of their respective nominal regulation voltage. overvoltage protection (ovp) when the buck output voltage rises above 120% of the nominal regulation voltage, the ovp circuit sets the fault latch, shuts down the pwm controller, and immedi- ately pulls dh low and forces dl high. the negative current limit is also disabled. this turns on the low-side mosfet, which rapidly discharges the output capaci- tors and clamps the output to ground. note that imme- diately latching dl high can cause the output voltage to go slightly negative due to energy stored in the out- put lc at the instant the ovp occurs. if the load cannot tolerate a negative voltage, place a power schottky diode from the output to pgnd (anode to pgnd) to act as a reverse-polarity clamp. cycle en or input power to reset the latch. overcurrent protection the current-limit circuit employs a unique valley cur- rent-sensing algorithm that uses the on-resistance of the low-side mosfet as a current-sensing element. if the current-sense signal is above the current-limit threshold, the pwm is not allowed to initiate a new cycle. the actual peak current is greater than the cur- rent-limit threshold by an amount equal to the inductor ripple current ( figure 4). therefore, the exact current- limit characteristic and maximum load capability are a function of the mosfet on-resistance, the inductor value, and the input voltage. the reward for this uncer- tainty is robust, lossless overcurrent sensing. there is also a negative current limit that prevents excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approxi- mately 110% of the positive current limit, and therefore tracks the positive current limit when ilim is adjusted. the current-limit threshold can be adjusted with an external resistor (r ilim ) at ilim. a precision 5a pullup current source at ilim sets a voltage drop on this resis- tor, adjusting the current-limit threshold from approxi- mately 50mv to 200mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/10 the volt- age seen at ilim. therefore, choose r ilim equal to 2k ? /mv of the current-limit threshold. the threshold defaults to 100mv when ilim is connected to vl. the logic threshold for switchover to the 100mv default value is approximately v vl - 1v. the adjustable current limit can accommodate various mosfets. alternately, foldback current limit can also be implemented by adding a resistor from ilim to v out . see the setting the current limit section.
carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the cur- rent-sense signals seen by lx and pgnd. the ic must be mounted close to the low-side mosfet with short, direct traces making a kelvin-sense connection to the source and drain terminals. see the pc board layout section. voltage positioning the quick-pwm control architecture responds virtually instantaneously to transient load changes and elimi- nates the control loop delay of conventional pwm con- trollers. therefore, a large portion of the voltage deviation during a step load change is from the esr (equivalent series resistance) of the output capacitors. for ddr termination applications, the maximum allowed voltage deviation is 40mv for any output load transition from sourcing current to sinking current. passive voltage positioning adjusts the converter s out- put voltage based on its load current to optimize tran- sient response and minimize the required output capacitance. voltage positioning is implemented by connecting a low ohmic resistor (r4) as shown in figure 2. mosfet drivers the dh and dl drivers are optimized to drive mosfets that can deliver up to 25a output current. an adaptive dead-time circuit monitors the dl output and prevents the high-side mosfet from turning on until dl is fully off. there must be a low-resistance, low- inductance path from the dl driver to the mosfet gate in order for the adaptive dead-time circuit to work prop- erly. otherwise, the sense circuitry in the max8553/ MAX8554 can interpret the mosfet gate as off while there is actually still charge left on the gate. use very short, wide traces measuring 10 squares to 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the max8553/MAX8554). this adaptive dead-time delay is in addition to a fixed delay of 30ns (typ). the dead time at the other edge (dh turning off) is determined by a fixed 32ns (typ) internal delay. design procedure setting the output voltage for the max8553, the output voltage, v vtt , is always 50% of v refin . for the MAX8554, the output voltage can be adjusted from 600mv to 3.5v using a resistive voltage-divider (r2 and r3 in figures 1 and 3). to set the voltage, choose a value for r3 in the range of 1k ? to 10k ? , then solve for r2 using the following equation: where v fb is 0.6v. inductor selection three key inductor parameters must be specified: inductance value (l), peak inductor current (i peak ), and dc resistance (r dc ). a good compromise between size and efficiency is to set the inductor peak- to-peak ripple current equal to 30% of the maximum load current, thus lir = 0.3. the switching frequency, input voltage, output voltage, and selected lir deter- mine the inductor value as follows: where f s is the switching frequency. the exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. lower inductor values minimize size and cost and also improve transient response but reduce efficiency and increase output voltage ripple due to higher peak cur- rents. higher inductance increases efficiency by reduc- ing the rms current. find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. the inductor s current saturation rating must exceed the l vvv v x f x i x lir out in out in s load max = () ? () rr v v out fb 23 = ? ? ? ? ? ? - 1 max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 18 ______________________________________________________________________________________ time inductor current i valley i load i peak figure 4. inductor-current waveform
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications ______________________________________________________________________________________ 19 peak inductor current at the maximum-defined load current (i load(max) ): output-capacitor selection the key selection parameters for the output capacitor are the actual capacitance value, the esr, the equiva- lent series inductance (esl), and the voltage-rating requirements, which affect the overall stability, output ripple voltage, and transient response. the worst-case output ripple has three components: variations in the charge stored in the output capacitor, the voltage drop across the capacitor s esr, and esl caused by the current into and out of the capacitor. this can be approximated by: the output voltage ripple due to the esr is: the output voltage ripple due to the output capacitance is: the output voltage ripple due to the esl of the output capacitor is: v ripple (esl) = (v in x esl) / (l+esl) i p-p is the peak-to-peak inductor current: after a load transient, the output voltage instantly changes by esr x ? i load + esl x di/dt and the con- trollers respond within 100ns and try to regulate back to the nominal output value. solid polymer or oscon electrolytic capacitors are recommended due to their low esr and esl at the switching frequency. higher output-current applications require multiple output capacitors connected in parallel to meet the output ripple-voltage requirements. do not exceed the capacitor s voltage or ripple-current ratings. output-capacitor stability consideration stability is determined by the value of the esr zero rel- ative to the switching frequency. to ensure stability, the following condition must be met: where f s is the switching frequency and: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. do not put high-value ceramic capacitors directly across the feedback sense point without taking precau- tions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage-ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under- or overshoot. input-capacitor selection the input capacitor (c in ) reduces the current peaks drawn from the input supply and reduces noise injec- tion. the source impedance to the input supply largely determines the value of c in . high source impedance requires high input capacitance. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the rms input rip- ple current is given by: i rms has a maximum value of 1/2 i load , which occurs when v in is twice v out . for optimal circuit reliability, choose a capacitor that has less than 10 c temperature rise at the peak ripple current. ii vvv v rms load out in out in = () - f rc esr esr out = 1 2 f f esr s < i v v v pp in out out in - s -v fl = v i cf ripple c pp out s () = - 8 v i esr ripple esr p p () = - vv v v ripple ripple esr ripple c ripple esl () () () =++ ii lir i peak load max load max () () =+ ? ? ? ? ? ? 2
setting the current limit constant current limit the adjustable current limit accommodates mosfets with a wide range of on-resistance values. the current- limit threshold is adjusted with an external resistor con- nected from ilim to gnd (r ilim_ ). the adjustment range is 50mv to 200mv measured across the low-side mosfet. the value of r ilim is calculated using the fol- lowing formula: where i valley is the valley current limit and r ds(on) is the on-resistance of the low-side mosfet. to avoid reaching the current at a lower current than expected, use the maximum value for r ds(on) at elevated junc- tion temperature. refer to the mosfet manufacturer s data sheet for maximum values. foldback current limit foldback current limit is used to reduce power dissipa- tion during overload and short-circuit conditions. this is accomplished by lowering the current-limit threshold as the output voltage drops due to the overload. to use foldback current limit, connect a resistor (r fobk ) from ilim to the output, and connect a resistor (r ilim ) from ilim to gnd ( figure 5). the values of r ilim and r fobk are calculated as follows: first, select the percentage of foldback, p fb . this per- cent corresponds to the current limit when v out equals zero divided by the current limit when v out equals its nominal voltage. typical values range from 15% to 30%. to solve for the resistor values, use the following equations: if r ilim results in a negative number, select another low- side mosfet with lower r ds(on) or increase p fb or a combination of both for the best compromise of cost, efficiency, and lower short-circuit power dissipation. adjusting the switching frequency the switching frequency of the max8553/MAX8554 can be lowered from the value set by fsel by adding a resistor voltage-divider to en/hsd (hsd) as shown in figure 6. this voltage-divider lowers the voltage the ic measures on en/hsd (hsd), which increases the on- time. the switching frequency with the added resistor- divider is calculated as follows: where k = 1.7s and n is given in tables 1 and 2. to set the frequency, select a value for r2 between 10k ? and 100k ? , then calculate r1 from the following equation: with the minimum input voltage, make sure that the voltage present at en/hsd (hsd) is greater than 1.5v when the resistor-divider is used: vr rr v in min () . + > 2 12 15 r kn r f r s 1 12 2 = - f kn r rr s ? + 12 12 r ri pr vri p ilim ds on valley fb fobk out ds on valley fb = () () () () () 10 1 10 1 - -- r pv ap fobk fb out fb = () 51 - r i a r ilim valley ds on = () 10 5 max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 20 ______________________________________________________________________________________ max8553 dh r ilim r fobk v out lx dl pgnd ilim figure 5. setting the foldback current limit with two resistors, r ilim and r fobk
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications ______________________________________________________________________________________ 21 setting voltage positioning the droop resistor, r drp (r4) in figure 2, in series with the output inductor before the output capacitor, sets the droop voltage, v drp . choose r drp such that the output voltage at the maximum load current, including ripple, is just above the lower limit of the output tolerance: r drp introduces some power dissipation, which is given by: r drp should be chosen to handle this power dissipation. power mosfet selection the max8553/MAX8554 drive external, logic-level, n- channel mosfets as the circuit-switch elements. the key selection parameters are: on-resistance (r ds(on) ): the lower, the better. maximum drain-to-source voltage (v dss ): this should be at least 20% higher than the input supply rail at the high-side mosfet s drain. gate charges (q g , q gd , q gs ): the lower, the better. choose the mosfets with rated r ds(on) at v gs = 4.5v. for a good compromise between efficiency and cost, choose the high-side mosfet that has a conduction loss equal to switching loss at nominal input voltage and maximum output current (see below). for the low-side mosfet, make sure that it does not spuriously turn on because of the dv/dt caused by the high-side mosfet turning on, as this would result in shoot-through current degrading the efficiency. mosfets with a lower q gd to q gs ratio have higher immunity to dv/dt. for proper thermal-management design, calculate the power dissipation at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for low-side mosfet, worst case is at v in(max) ; for high-side mosfet, it could be either at v in(min) or v in(max) ). the high-side mosfet and low-side mosfet have different loss components due to the circuit operation. the low-side mosfet operates as a zero voltage switch; therefore, major losses are: the channel conduction loss (p lscc ), the body-diode conduction loss (p lsdc ), and the gate- drive loss (p lsdr ): use r ds(on) at t j(max): where v f is the body-diode forward-voltage drop, t dt is the dead time (~30ns), and f s is the switching frequency. because of the zero-voltage switch operation, low-side mosfet gate-drive loss occurs as a result of charging and discharging the input capacitance (c iss ). this loss is distributed among the average dl gate driver s pullup and pulldown resistance, r dl (~1.2 ? ), and the internal gate resistance (r gate ) of the mosfet (~2 ? ). the drive power dissipated is given by: the high-side mosfet operates as a duty-cycle con- trol switch and has the following major losses: the channel conduction loss (p hscc ), the vi overlapping switching loss (p hssw ), and the drive loss (p hsdr ). the high-side mosfet does not have body-diode con- duction loss because the diode never conducts current. pcvf r rr lsdr iss gs s gate gate dl = () + 2 pivtf lsdc load f dt s = 2 p v v ir lscc out in load ds on = ? ? ? ? ? ? () () 1 2 - pri d drp drp out max () ( ) = () 2 r vvv i drp out typ out min ripple out max < / () () () - - 2 max8553 gnd fsel ilim ref en/hsd refin v+ pok vttr vtt pgnd dl lx dh bst vl r2 r6 10k ? q3 2n7002 sdn r1 vin figure 6. a resistor-divider (r1 and r2) is used to lower the switching frequency.
use r ds(on) at t j(max) : where i gate is the average dh driver output current determined by: where r dh is the high-side mosfet driver s on-resis- tance (1.4 ? typ) and r gate is the internal gate resis- tance of the mosfet (~2 ? ): where v gs = v vl = 5v. when the max8553 is sinking current, the high-side mosfet operates as a zero-voltage switch and the low-side mosfets operate as a nonzero-voltage switch. in addition to the losses above, allow about 20% more for additional losses due to mosfet output capaci- tances and low-side mosfet body-diode reverse recovery charge dissipated in the high-side mosfet that is not well defined in the mosfet data sheet. refer to the mosfet data sheet for thermal-resistance speci- fications to calculate the pc board area needed to maintain the desired maximum operating junction tem- perature with the above calculated power dissipations. to reduce emi caused by switching noise, add a 0.1f ceramic capacitor from the high-side switch drain to the low-side switch source, or add resistors in series with dh and dl to slow down the switching transitions. adding series resistors increases the power dissipation of the mosfet, so ensure that this does not overheat the mosfet. control ic power dissipation power dissipation in the max8553/MAX8554 ic is pri- marily due to the on-chip mosfets gate drivers (dh and dl). this power dissipation depends on the gate charge of the external mosfets used. power dissipa- tion in the max8553 also depends on the vttr load current (i vttr ). use the following equation to calculate the power dissipation: where q gh and q gl are the total gate charge of the high-side and low-side mosfets, respectively. select the switching frequency and v v+ correctly to ensure the power dissipation does not exceed the package power-dissipation requirement. applications information pc board layout a properly designed pc board layout is important in any switching regulator. the switching power stage requires particular attention. if possible, mount all the power components on the top-side of the board with their ground terminals flush against one another. follow these guidelines for good pc board layout: 1) keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, low-jitter operation. 2) connect gnd and pgnd together at a single point. 3) keep the power traces and load connections short. this practice is essential for high efficiency. the use of thick copper pc boards (2oz vs. 1oz) can notice- ably enhance full-load efficiency. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance caus- es a measurable efficiency penalty. 4) lx and pgnd connections to the low-side mosfet for current limiting must be made using kelvin- sense connections in order to guarantee the cur- rent-limit accuracy. with 8-pin so mosfets, this can be done by routing power to the mosfets from pv fq q i d v s gh gl vttr = () + () + [] + pqvf r rr hsdr g gs s gate gate dh = + i v rr gate dh gate = + 25 . pvif qq i hssw in load s gs gd gate = + p v v ir hscc out in load ds on = () () 2 max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications 22 ______________________________________________________________________________________
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications ______________________________________________________________________________________ 23 pin configurations outside using the top copper layer, while tying in pgnd and lx inside (underneath) the 8-pin so package. 5) when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. 6) it may be desirable to deliberately introduce some trace length (droop resistance) between the fb inductor node and the output filter capacitor to meet the stability criteria (f esr < f s / ). 7) place feedback resistors as close as possible to the ic. 8) route high-speed switching nodes away from sen- sitive analog nodes. 9) make all pin-strap control input connections (ilim, etc.) to gnd or vl close to the chip, and do not connect to pgnd. chip information transistor count: 2827 process: bicmos 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 en/hsd lx dh bst pgnd dl vl v+ vttr top view max8553 qsop refin pok fsel vtt ilim ref gnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 hsd lx dh bst pgnd dl vl v+ out MAX8554 qsop en pok fsel fb ilim ref gnd
max8553/MAX8554 4.5v to 28v input, synchronous pwm buck controllers for ddr termination and point-of-load applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch

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